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IS63LV1024 IS63LV1024L
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
FEATURES
* High-speed access times: 8, 10, 12 ns * High-performance, low-power CMOS process * Multiple center power and ground pins for greater noise immunity * Easy memory expansion with CE and OE options * CE power-down * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 3.3V power supply * Packages available: - 32-pin 300-mil SOJ - 32-pin 400-mil SOJ - 32-pin TSOP (Type II) - 32-pin STSOP (Type I) - 36-pin BGA (8mmx10mm) * Lead-free Available
JANUARY 2007
DESCRIPTION
The ISSI IS63LV1024/IS63LV1024L is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM in revolutionary pinout. The IS63LV1024/IS63LV1024L is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 W (typical) with CMOS input levels. The IS63LV1024/IS63LV1024L operates from a single 3.3V power supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K X 8 MEMORY ARRAY
VDD GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. I 1/26/07
1
IS63LV1024 IS63LV1024L
PIN CONFIGURATION
32-Pin SOJ
PIN CONFIGURATION
32-Pin TSOP (Type II) (T) 32-Pin STSOP (Type I) (H)
A0 A1 A2 A3 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8
A0 A1 A2 A3 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8
PIN DESCRIPTIONS
A0-A16 CE OE WE I/O0-I/O7 VDD GND Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Inputs/Outputs Power Ground
PIN CONFIGURATION
36-mini BGA (B) (8 mm x 10 mm)
1 2 3 4 5 6
A B C D E F G H
A0 I/O4 I/O5 GND VDD I/O6 I/O7 A9
A1 A2
NC WE NC
A3 A4 A5
A6 A7
A8 I/O0 I/O1 VDD GND
NC OE A10 CE A11
NC A16 A12 A15 A13
I/O2 I/O3 A14
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. I 1/26/07
IS63LV1024 IS63LV1024L
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG PT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value -0.5 to VDD + 0.5 -65 to +150 1.0 Unit V C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V 0.3V 3.3V 0.15V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VDD GND VOUT VDD, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 -- 2.2 -0.3 -1 -5 -1 -5 Max. -- 0.4 VDD + 0.3 0.8 1 5 1 5 Unit V V V V A A
Notes: 1. VIL = -3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. I 1/26/07
3
IS63LV1024 IS63LV1024L
IS63LV1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC1 VDD Operating Supply Current Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = Max. Com. Ind. typ.(2) Ind. (@15 ns) Com. Ind. Com. Ind. Com. Ind. typ.(2) -8 ns Min. Max. -- -- -- -- -- -- -- -- -- -- 160 170 105 55 55 25 30 5 10 0.5 -10 ns Min. Max. -- -- -- -- -- -- -- -- -- -- 150 160 95 45 45 25 30 5 10 0.5 -12 ns Min. Max. -- -- -- -- -- -- -- -- -- -- -- 130 140 75 90 40 40 25 30 5 10 0.5 Unit mA
ISB
TTL Standby Current (TTL Inputs) TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs)
VDD = Max., VIN = VIH or VIL CE VIH, f = Max VDD = Max., VIN = VIH or VIL CE VIH, f = 0 VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0
mA
ISB1
mA
ISB2
mA
Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested.
IS63LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC1 VDD Operating Supply Current TTL Standby Current (TTL Inputs) TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = Max. VDD = Max., VIN = VIH or VIL CE VIH, f = Max VDD = Max., VIN = VIH or VIL CE VIH, f = 0 VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0 Com. Ind. typ.(2) Com. Ind. Com. Ind. Com. Ind. typ.(2) -8 ns Min. Max. -- -- -- -- -- -- -- -- -- -- 100 110 75 35 40 15 20 1 1.5 0.05 -10 ns Min. Max. -- -- -- -- -- -- -- -- -- -- 95 105 70 30 35 15 20 1 1.5 0.05 -12 ns Min. Max. -- -- -- -- -- -- -- -- -- -- 90 100 65 25 30 15 20 1 1.5 0.05 Unit mA
ISB
mA
ISB1
mA
ISB2
mA
Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested.
CAPACITANCE(1,2)
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
4
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Rev. I 1/26/07
IS63LV1024 IS63LV1024L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power Up Time CE to Power Down Time -8 ns Min. Max. 8 -- 2 -- -- 0 0 3 0 0 -- -- 8 -- 8 4 -- 4 -- 4 -- 8 -10 ns Min. Max. 10 -- 2 -- -- 0 0 3 0 0 -- -- 10 -- 10 5 -- 5 -- 5 -- 10 -12 ns Min. Max. 12 -- 2 -- -- 0 0 3 0 0 -- -- 12 -- 12 6 -- 6 -- 6 -- 12 Unit ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tLZOE(2) tHZOE(2) tLZCE tPU tPD
(2) (2)
tHZCE
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V loading specified in Figure 1. 2. Tested with the loading specified in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
AC TEST LOADS
317
ZOUT = 50 OUTPUT 50 VT = 1.5V
Figure 1 Figure 2
3.3V
OUTPUT 5 pF Including jig and scope 351
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Rev. I 1/26/07
5
IS63LV1024 IS63LV1024L
AC WAVEFORMS READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
OE
t OHA
t DOE
CE
t HZOE
t LZOE t ACE t LZCE t HZCE
DATA VALID
CE_RD2.eps
DOUT
HIGH-Z
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
6
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Rev. I 1/26/07
IS63LV1024 IS63LV1024L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time
(1)
-8 ns Min. Max. 8 7 8 0 0 7 8 5 0 -- 3 -- -- -- -- -- -- -- -- -- 4 --
-10 ns Min. Max. 10 7 8 0 0 7 10 5 0 -- 3 -- -- -- -- -- -- -- -- -- 5 --
-12 ns Min. Max. 12 8 8 0 0 8 12 6 0 -- 3 -- -- -- -- -- -- -- -- -- 6 --
Unit ns ns ns ns ns ns ns ns ns ns ns
tWC tSCE tAW tHA tSA tPWE1 tSD tHD tHZWE
(2)
WE Pulse Width (OE High) WE Pulse Width (OE Low) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
tPWE2(2)
tLZWE(2)
Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
AC WAVEFORMS WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t HZWE t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
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Rev. I 1/26/07
7
IS63LV1024 IS63LV1024L
AC WAVEFORMS WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW t PWE1
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
CE_WR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS OE CE
VALID ADDRESS
LOW
t HA
LOW
t AW t PWE2
WE
tSA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH.
8
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Rev. I 1/26/07
IS63LV1024 IS63LV1024L
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 2.0V, CE VDD - 0.2V See Data Retention Waveform See Data Retention Waveform
O
Options IS63LV1024 IS63LV1024L
Min. 2.0 -- -- 0
Typ.(1) -- 0.5 0.05 -- --
Max. 3.6 10 1.5 -- --
Unit V mA ns ns
VDR
IDR
tSDR tRDR
tRC
Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR VDD
Data Retention Mode
tRDR
VDR CE VDD - 0.2V
CE GND
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Rev. I 1/26/07
9
IS63LV1024 IS63LV1024L
IS63LV1024 ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 8 10 Order Part No. IS63LV1024-8K IS63LV1024-8KL IS63LV1024-10T IS63LV1024-10J IS63LV1024-10K IS63LV1024-12T IS63LV1024-12J IS63LV1024-12KL Package 400-mil Plastic SOJ 400-mil Plastic SOJ, Lead-free TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ, Lead-free
12
Industrial Range: -40C to +85C
Speed (ns) 8 10 12 Order Part No. IS63LV1024-8KI IS63LV1024-10KI IS63LV1024-12TI Package 400-mil Plastic SOJ 400-mil Plastic SOJ TSOP (Type II)
10
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Rev. I 1/26/07
IS63LV1024 IS63LV1024L
IS63LV1024L ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 8 10 Order Part No. IS63LV1024L-8T IS63LV1024L-8B IS63LV1024L-10T IS63LV1024L-10TL IS63LV1024L-10HL IS63LV1024L-12T IS63LV1024L-12H IS63LV1024L-12J IS63LV1024L-12JL IS63LV1024L-12B Package TSOP (Type II) mBGA (8mmx10mm) TSOP (Type II) TSOP (Type II), Lead-free sTSOP (Type I) (8mm x13.4mm), Lead-free TSOP (Type II) sTSOP (Type I) (8mm x13.4mm) 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free mBGA (8mmx10mm)
12
Industrial Range: -40C to +85C
Speed (ns) 8 Order Part No. IS63LV1024L-8TI IS63LV1024L-8JI IS63LV1024L-8KI IS63LV1024L-8BI IS63LV1024L-10HI IS63LV1024L-10JLI IS63LV1024L-10KLI IS63LV1024L-10TLI IS63LV1024L-12BI IS63LV1024L-12BLI IS63LV1024L-12TI Package TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ mBGA (8mmx10mm) sTSOP (Type I) (8mm x13.4mm) 300-mil Plastic SOJ, Lead-free 400-mil Plastic SOJ, Lead-free TSOP (Type II), Lead-free mBGA (8mmx10mm) mBGA (8mmx10mm), Lead-free TSOP (Type II)
10
12
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Rev. I 1/26/07
11
PACKAGING INFORMATION
400-mil Plastic SOJ Package Code: K
N
N/2+1
E1
E
Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027.
1
N/2
D A
SEATING PLANE
b
C A2
e
B
A1
E2
Symbol No. Leads A A1 A2 B b C D E E1 E2 e
Millimeters Inches Min Max Min Max (N) 28 3.25 3.75 0.128 0.148 0.64 -- 0.025 -- 2.08 -- 0.082 -- 0.38 0.51 0.015 0.020 0.66 0.81 0.026 0.032 0.18 0.33 0.007 0.013 18.29 18.54 0.720 0.730 11.05 11.30 0.435 0.445 10.03 10.29 0.395 0.405 9.40 BSC 0.370 BSC 1.27 BSC 0.050 BSC
Millimeters Min Max 32 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 20.82 21.08 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC
Inches Min Max 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 0.820 0.830 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC
Millimeters Min Max 36 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 23.37 23.62 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC
Inches Min Max 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 0.920 0.930 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 10/29/03
PACKAGING INFORMATION
Millimeters Inches Symbol Min Max Min Max No. Leads (N) 40 A 3.25 3.75 0.128 0.148 A1 0.64 -- 0.025 -- A2 2.08 -- 0.082 -- B 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 E 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC Millimeters Min Max 42 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 27.18 27.43 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 1.070 1.080 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Millimeters Min Max 44 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 28.45 28.70 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Inches Min Max
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
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Rev. F 10/29/03
PACKAGING INFORMATION
300-mil Plastic SOJ Package Code: J
N
E1
E
1
D A
SEATING PLANE
B
A2 C
e
b
A1
E2
MILLIMETERS Sym.
N0. Leads A A1 A2 b B C D E E1 E2 e -- 0.64 2.41 0.41 0.66 0.20 17.02 8.26 7.49 6.27
INCHES Min. Typ. Max.
Min. Typ. Max.
24/26 -- -- -- -- -- -- -- -- -- -- 3.56 -- 2.67 0.51 0.81 0.25 17.27 8.76 7.75 7.29
Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of
the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
-- 0.025 0.095 0.016 0.026 0.008 0.670 0.325 0.295 0.247
-- 0.140 -- -- -- -- -- -- -- -- -- -- 0.105 0.020 0.032 0.010 0.680 0.345 0.305 0.287
1.27 BSC
0.050 BSC
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 02/25/03
PACKAGING INFORMATION
300-mil Plastic SOJ Package Code: J
MILLIMETERS Sym.
N0. Leads A A1 A2 b B C D E E1 E2 e -- 0.64 2.41 0.41 0.66 0.20 18.29 8.26 7.49 6.27
INCHES Min. Typ. Max. Sym.
N0. Leads
MILLIMETERS Min. Typ. Max.
32 -- 0.64 2.41 0.41 0.66 0.20 20.83 8.26 7.49 6.27 -- -- -- -- -- -- -- -- -- -- 3.56 -- 2.67 0.51 0.81 0.25 21.08 8.76 7.75 7.29 --
INCHES Min. Typ. Max.
Min. Typ. Max.
28 -- -- -- -- -- -- -- -- -- -- 3.56 -- 2.67 0.51 0.81 0.25 18.54 8.76 7.75 7.29
-- 0.025 0.095 0.016 0.026 0.008 0.720 0.325 0.295 0.247
-- -- -- -- -- -- -- -- -- --
0.140 -- 0.105 0.020 0.032 0.010 0.730 0.345 0.305 0.287
A A1 A2 b B C D E E1 E2 e
-- -- -- -- -- -- -- -- -- --
0.140 -- 0.105 0.020 0.032 0.010 0.830 0.345 0.305 0.287
0.025 0.095 0.016 0.026 0.008 0.820 0.325 0.295 0.247
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
2
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Rev. D 02/25/03
PACKAGING INFORMATION
Plastic STSOP - 32 pins Package Code: H (Type I)
A2 A A1 1 N
E
b
e D1 D S
SEATING PLANE
L
C
Plastic STSOP (H - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 32 A -- 1.25 -- 0.049 A1 0.05 -- 0.002 -- A2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 C 0.14 0.16 0.0055 0.0063 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 e 0.50 BSC 0.020 BSC L 0.30 0.70 0.012 0.028 S 0.28 Typ. 0.011 Typ. 0 5 0 5
Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
Integrated Silicon Solution, Inc.
PK13197H32 Rev. B 04/21/03
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: B (36-pin)
Top View 1 2 3 4 56 6 Bottom View
b (36x)
5
4
3
2
1
A B C D D E F G H D1
e
A B C D E F G H
e E E1
Notes: 1. Controlling dimensions are in millimeters.
A2 SEATING PLANE A1 A
mBGA - 6mm x 8mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b 5.90 -- 0.24 0.60 7.90
mBGA - 8mm x 10mm
INCHES Min. Typ. Max.
36
MILLIMETER Sym.
N0. Leads
INCHES Min. Typ. Max.
36
Min. Typ. Max.
36 -- -- -- 8.00 5.25BSC 6.00 6.10 3.75BSC 0.75BSC 0.30 0.35 0.40 1.20 0.30 -- 8.10
Min. Typ. Max.
36 -- 0.24 0.60 -- -- -- 5.25BSC 7.90 8.00 8.10 3.75BSC 0.75BSC 0.30 0.35 0.40 1.20 0.30 --
-- 0.009 0.024
-- -- --
0.047 0.012 --
A A1 A2 D D1 E E1 e b
-- 0.009 0.024
-- -- --
0.047 0.012 --
0.311 0.315 0.319 0.207BSC 0.232 0.236 0.240 0.148BSC 0.030BSC 0.012 0.014 0.016
9.90 10.00 10.10
0.390 0.394 0.398 .207BSC 0.311 0.315 0.319 0.148BSC 0.030BSC 0.012 0.014 0.016
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 01/15/03
PACKAGING INFORMATION
Plastic TSOP Package Code: T (Type II)
N
N/2+1
E1
E
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
1 D
N/2
SEATING PLANE
ZD
A
.
e b L A1 C
Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD
Millimeters Min Max
Inches Min Max
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0 5 0 5
Millimeters Min Max 50 -- 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0 5
Inches Min Max
(N) 32 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0 5 0 5
-- 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0 5
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 06/18/03

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